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The ARM architecture (originally the Acorn RISC Machine) is a 32-bit RISC processor architecture that is widely used in a number of applications. ARM variants are in widespread use in embedded and low-power applications due to their power saving design features.

The ARM chip has become one of the most used CPU designs in the world, found in everything from hard drives, to mobile phones, to routers, to calculators, to children's toys. Today it accounts for over 75% of all 32-bit embedded CPUs. It is the processor found in all iPods and iPod Nanos.

History

The ARM design was started in 1983 as a development project at Acorn Computers Ltd.

The team, led by Roger Wilson and Steve Furber, started development of what in some ways represents an advanced MOS Technology 6502. Acorn had a long line of computers based on the 6502, so a chip that was similar to program could represent a significant advantage for the company.

The team completed development samples called ARM1 by 1985, and the first "real" production systems as ARM2 the following year. The ARM2 featured a 32-bit data bus, a 26-bit address space and 16 32-bit registers. One of these registers served as the (word aligned) program counter with its top 6 bits and lowest 2 bits holding the processor status flags. The ARM2 was possibly the simplest useful 32-bit microprocessor in the world, with only 30,000 transistors (compare with Motorola's four-year older 68000 with around 68,000). Much of this simplicity comes from not having microcode (which represents about 1/4 to 1/3rd of the 68000) and, like most CPUs of the day, not including any cache. This simplicity lead to its low power usage, while performing better than the 286. A successor, ARM3, was produced with a 4KB cache which further improved performance.

In the late 1980s Apple Computer started working with Acorn on newer versions of the ARM core. The work was so important that Acorn spun off the design team in 1990 into a new company called Advanced RISC Machines. For this reason you often see ARM lengthened to Advanced RISC Machine instead of Acorn RISC Machine. Advanced RISC Machines became ARM Limited when the company floated on the London Stock Exchange and NASDAQ in 1998.

This work would eventually turn into the ARM6. The first models were released in 1991, and Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA. In 1994, Acorn used the ARM 610 as the main CPU in their RiscPC computers.

The core has remained largely the same size throughout these changes. ARM2 had 30,000 transistors, while the ARM6 grew to only 35,000. The idea is that the end-user combines the ARM core with a number of optional parts to produce a complete CPU, one that can be built on old semiconductor fabs and still deliver lots of performance at a low cost.

The most successful implementation has been the ARM7TDMI with hundreds of millions sold in mobile phones, handheld video game systems, and Sega Dreamcasts. While ARM's business has always been to sell IP cores, some of the licensees generated microcontrollers based on this core.

DEC licensed the architecture (which caused some confusion because they also produced the DEC Alpha) and produced the StrongARM
. At 233MHz this CPU drew only 1 watt of power (more recent versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their aging i960 line with the StrongARM. Intel have since developed its own high performance implementation known by the name XScale
.

Freescale (spun off from Motorola in 2004), IBM, Infineon Technologies, Texas Instruments, Nintendo, Philips, VLSI, Atmel, Sharp, Samsung and STMicroelectronics have also licensed the basic ARM design for various uses.

The cores

Design notes

To keep the design lean, simple and fast, it was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers.

The ARM architecture includes the following RISC features:

Three-address architecture
Load/store architecture
No support for misaligned memory accesses
Orthogonal instruction set
Large 16 × 32-bit register file
Fixed opcode width of 32 bits to ease decoding and pipelining, at the cost of decreased code density
Mostly single-cycle execution

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