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The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting functions. They are found in all x86 PCs.

History

In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard's southbridge chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIC using the x86 I/O address space. Reads and writes to such a PIC's registers in the I/O address space may complete much faster.

Newer x86 PICs include a counter through the Advanced Configuration and Power Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and a Time Stamp Counter (TSC) introduced on the Pentium.

Features

The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.

Typical Components

Counters

There are 3 counters (or timers), which are labelled as Counter 0, Counter 1 and Counter 2. Each counter has 2 input pins - CLK (clock input) and GATE - and 1 pin, OUT, for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.

The first counter (selected by setting D7=D6=0, see Control Word Register below) helps generate a 18.2 Hz clock signal. The second counter (D7=0, D6=1) assists in generating timing, which will be used to refresh the DRAM memory. The last counter (D7=1, D6=0) generates tones for the PC speaker.

Besides the counters, a typical Intel 8253 chipset also contains the following components:

Data/Bus Buffer

This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.

Read/Write Logic

The Read/Write Logic block has 5 pins, which are listed below. Notice that X\ denotes an active low signal.

RD\: read signal
WR\: write signal
CS\: chip select signal
A0, A1: address lines

Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set CS\=0, RD\=1, WR\=0, A1=A0=1.

Control Word Register

This register contains the programmed information which will be sent (by the microprocessor) to the device. It defines how the PIT logically works.

To initialise the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data/Bus Buffer block.

The control word contains 8 bits, label D7..D0 (D7 is the MSB).

Bit#   D7   D6    D5   D4     D3  D2  D1    D0
Name   SC1  SC0   RW1  RW0    M2  M1  M0    BCD
-----  --------   ----------  -----------   ------------------------
Func.  Select     Read/Write  Select        =0, 16-b binary counter
       Counter                Mode          =1, 4-decade BCD counter

The following table describes how to use the Read/Write bits (RW1, RW0).

RW1   RW0   Description
---   ---   ------------------------------------------------
0     0     Counter Latch Command
0     1     Read/Write the least significant byte (LSB) only
1     0     Read/Write the most significant byte (MSB) only
1     1     Read/Write LSB first, followed by MSB

Details about other bits will be provided in the next section.

During a typical rountine with the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.

On most PCs, the address for Control Word Register is 043 hex, and 040h, 041h, 042h for each counter.

Operation Modes

Operation mode is set using the D3, D2, D1 bytes of the Control Word. There are 5 modes in total. Notice that, for modes 0, 2 and 3, GATE must be set to HIGH to enable counting. For details on each mode, see the reference links.

=== Mode 0 (D3=D2=D1=0) (Interrupt on Terminal Count) === In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.

The OUT pin is set to 0 after the Control Word is received, and counting starts one clock cycle after the COUNT message is received. OUT remains low until the counter reaches 0. Once then, OUT will be set to high until the counter is reloaded or the Control Word is written.

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